The present invention relates to solid-state imaging devices, e.g., CMOS image sensors or CCD image sensors. The invention also relates to electronic apparatus including a solid-state imaging device, and a method for manufacturing a solid-state imaging device.
Solid-state imaging devices, for example, complementary metal-oxide semiconductor (CMOS) image sensors and charge coupled device (CCD) image sensors, have been developed previously. A solid-state imaging device has a configuration, in which a photodiode (photoelectric conversion element) is disposed on the surface of a semiconductor substrate and when light is incident on the photodiode, an image signal is obtained on the basis of a signal charge generated in the photodiode. Furthermore, regarding a solid-state imaging device having the above-described configuration, in order to improve the optical characteristics, various configurations have been proposed previously (refer to Japanese Unexamined Patent Application Publication Nos. 2000-150846 and 2004-273791, for example).
FIG. 26 shows a schematic configuration sectional view of a solid-state imaging device proposed in Japanese Unexamined Patent Application Publication No. 2000-150846. A solid-state imaging device 100 described in this document is composed of a light-receiving portion 101 including photoelectric conversion elements 104 arranged on the surface of a semiconductor substrate 103 one-dimensionally or two-dimensionally and a peripheral circuit portion 102 disposed in the periphery thereof. Furthermore, the solid-state imaging device 100 is provided with microlenses 108 and/or a color filters 107 disposed on the light-receiving portion 101 with an interlayer film 111 and wirings 105 therebetween. In this regard, the interlayer film 111, an etching stopper layer 112, a protective film 113, and a wiring layer including wirings 106 are disposed on the semiconductor substrate 103 of the peripheral circuit portion 102.
Moreover, regarding the solid-state imaging device 100 described in Japanese Unexamined Patent Application Publication No. 2000-150846, the thickness di of the wiring layer of the light-receiving portion 101 is specified to be smaller than the thickness dc of the wiring layer of the peripheral circuit portion 102. Consequently, the light-condensing efficiency of the microlens 108 is improved and a color-mixing problem of the color filter 107 is avoided.
In addition, FIG. 27 shows a schematic sectional view in the vicinity of the boundary between a peripheral circuit portion and a sensor portion of a solid-state imaging device proposed in Japanese Unexamined Patent Application Publication No. 2004-273791. In the configuration of a solid-state imaging device 150 described in this document, a plurality of wiring layers 161 to 163 are laminated on a substrate 160 of a peripheral circuit portion 151 with flattening film layers 165 therebetween, and the surface height of the laminated layer is reduced stepwise toward a sensor portion 152. According to such a configuration, a sharp change in height at the boundary between the peripheral circuit portion 151 and the sensor portion 152 is reduced, and the film thickness of a predetermined upper layer 164 disposed on the sensor portion 152 is made almost uniform all over the surface of the sensor portion 152, so as to facilitate an improvement of the optical characteristics.
As described above, Japanese Unexamined Patent Application Publication Nos. 2000-150846 and 2004-273791 propose technologies to form a height difference at the boundary between the sensor portion and the peripheral circuit portion. In Japanese Unexamined Patent Application Publication No. 2004-273791, this technology is applied to a solid-state imaging device produced by an aluminum (Al) wiring process. This technology can also be applied to a solid-state imaging device produced by a copper (Cu) process.
FIG. 28, while not prior art, is an illustrative example of the problem encountered by the inventors. FIG. 28 depicts a configuration sectional view of a solid-state imaging device in the case where the above-described technology is applied to the solid-state imaging device produced by the Cu wiring process. In this regard, FIG. 28 shows a configuration example in the case where a solid-state imaging device 200 is a CMOS image sensor.
The solid-state imaging device 200 is provided with a semiconductor substrate 201 and a wiring layer portion including metal films 205 and light-shielding layers 206 deposited with interlayer insulating layers 203 and capping films 204 therebetween. Furthermore, the solid-state imaging device 200 is provided with a passivation film 207, a layer of color filter 208, and a layer of on-chip lens 209. Moreover, the wiring layer portion, the passivation film 207, the layer of color filter 208, and the layer of on-chip lens 209 are laminated on the semiconductor substrate 201 in that order. In this regard, FIG. 28 shows an example in which the wiring layer portion is composed of five wiring layers 1MT to 5MT.
In addition, the solid-state imaging device 200 is composed of a sensor portion region 220 and a peripheral circuit region 230 including, for example, a vertical drive circuit and a horizontal drive circuit on a semiconductor substrate 201. A plurality of pixels 240 including photodiodes 202 serving as photoelectric conversion elements and pixel transistors (MOS transistors: not shown in the drawing) are arranged two-dimensionally on the surface of the semiconductor substrate 201 in the sensor portion region 220.
Furthermore, the sensor portion region 220 includes an effective pixel region 221, which outputs image signals actually, and an invalid pixel region 222, which does not output an image signal actually. Moreover, the sensor portion region 220 includes an optical black region (hereafter referred to as OPB region) 223, which outputs a reference signal at a black level. In this regard, the invalid pixel region 222 and the OPB region 223 are disposed at desired locations in the periphery of the effective pixel region 221.
Then, in the solid-state imaging device 200, the thickness of the wiring layer portion 220a in the sensor portion region 220 is specified to be smaller than the thickness of the wiring layer portion 230a in the peripheral circuit region 230. Consequently, a height difference portion 210 is formed at the boundary between the sensor portion region 220 and the peripheral circuit region 230.
However, in the solid-state imaging device 200 having the above-described configuration, the light-shielding layers 206 in the OPB region 223 are disposed as layers above the wiring layer 2MT and, thereby, it is difficult to reduce the distance between the photodiode 202 and the on-chip lens 209 sufficiently. Consequently, regarding the solid-state imaging device 200 in the related art, a problem occurs in that the optical sensitivity of the photodiode 202 is not improved sufficiently.